1. Field of the Invention
The present invention relates generally to the polishing of semiconductor wafers utilizing chemical mechanical polishing technologies, and more particularly, the present invention relates to conditioning the surfaces of polishing pads used therein.
2. Background of the Related Art
The advances in integrated circuit device technology have necessitated the advancement of chemical mechanical polishing (CMP) technology to provide better and more consistent surface planarization processes. The manufacture of these devices (i.e. CMOS, VLSI, ULSI, microprocessors, semiconductor memory, and related technologies) on prepared substrates and the preparation of the substrates themselves (prime wafer polishing) require very highly planar and uniform surfaces. To achieve these high levels of planarity and uniformity on substrate surfaces, the processes that produce them must be performed reliably and consistently. Surfaces that are underpolished, overpolished, nonuniform, and/or nonplanar will not produce quality microelectronic devices.
In CMP fabrication techniques, a free abrasive chemical slurry is often used along with a rotating polishing pad, linear polishing belt, or rotating drum to contact the workpiece surface and to polish and planarize that surface. Typical examples of these types of apparatus are described in U.S. Pat. No. 5,329,732, assigned to SpeedFam disclosing a rotating polishing pad polisher; PCT Publication WO 97/20660, assigned to Applied Materials disclosing a linear belt polisher; and U.S. Pat. No. 5,643,056, assigned to Ebara Corporation and Kabushiki Kaisha Toshiba disclosing a rotating drum polisher. The disclosures of the foregoing patents, in relevant part, are incorporated herein by reference.
In such prior art polishing methods, one side of the wafer is attached to a wafer carrier and the other side of the wafer is pressed against a polishing surface. In general, the polishing surface comprises a polishing pad or belt that can be formed of various commercially available materials such as blown polyurethane from Rodel in Scottsdale, Ariz. Typically, a water-based colloidal abrasive slurry such as cerium oxide, aluminum oxide, fumed/precipitated silica or other particulate abrasives is deposited upon the polishing surface. During the polishing or planarization process, the workpiece (e.g., silicon wafer) is typically pressed against the moving (e.g., rotating or linearly translating) polishing surface. In addition, to improve the polishing effectiveness, the wafer may also be rotated about its vertical axis and/or oscillated over the inner and outer peripheries of the polishing surface. When pressure is applied between the polishing surface and the workpiece being polished, the combined abrasive particles and chemicals within the slurry produce mechanical abrasion and chemical corrosion of the surface being polished, thereby removing material from the workpiece.
However, a severe disadvantage to these methods is that any imperfections in the polishing surface will be transferred to the workpiece surface leading to a lessening of polishing planarity and uniformity of that workpiece. For these reasons, it is paramount not only to correct for degradation of the polishing surface due to wear but also to correctly prepare the surface prior to use. The recent and continuing advances in semiconductor technology, including the use of novel materials and decreasing size geometries, forces the need to more closely control the regularity of the polishing processes. In particular, the use of soft metals such as copper as a replacement for the harder aluminum and tungsten in metal interconnects often produces irregular, nonplanar, and nonuniform polishing results when using polishing surfaces conditioned by currently known processes. A second type of device structure, namely shallow trench isolation (STI), also has the same difficulties.
It has been generally understood that non-uniform surface wear and bulk deformation of the pad are the most significant causes of nonplanar and non-uniform polishing results. To alleviate this problem, multiple methods have been developed to recondition the surface of the pad. These methods are primarily abrasive in form as described in U.S. Pat. No. 5,486,131 assigned to SpeedFam that discloses an oscillating and rotating abrasive coated ring assembly. The most commonly used abrasive grains are diamonds, although many other "superabrasive" materials have been used (e.g., silicon nitride, "SuperNexus", CBN--cubic boron nitride). A strong disadvantage to the use of these abrasive coated assemblies is the use of the abrasive particles themselves. Often abrasive grains are freed from the conditioning assembly during use. When these grains become embedded into the pad, the result is a scratch in the workpiece. Because the abrasive grains are significantly harder than the workpiece surface layers, a single scratch can be severe and effectively destroy the workpiece. Moreover, the use of these abrasive assemblies for conditioning the polishing surfaces to control non-uniform and non-planar polishing of copper, STI and other structures has proven to be very unsatisfactory.
Two of the most significant problems arising from non-uniform and non-planar polishing are dishing and erosion. Examples of these defects in the copper damascene process resulting from a prior art CMP process are illustrated in FIG. 1. Briefly stated, the copper damascene process involves the overfilling of trench and via structures formed in an oxide layer and then polishing the copper material to form the required interconnects and via structures on the wafer. As shown in FIG. 1, dishing 10 in the copper interconnect features is evidenced by the nonplanar, typically concave, surface of copper lines between proximate underlying oxide features 30 on the workpiece surface. Erosion 20 occurs when there are insufficient oxide or stop layer 40 features to "stop" the CMP process from overpolishing the soft copper 50. Such defects formed during the polishing process cause difficulties in subsequent steps of the microelectronic device fabrication such as in lithographic process steps. Other significant problems caused by these defects include premature circuit failures and completely defective devices. Further information regarding the difficulties involved in copper processing and methods of monitoring such processes can be found in U.S. Pat. No. 5,723,874, assigned to International Business Machines Corporation in relevant part incorporated herein by reference.
Other known techniques for dealing with dishing and erosion include die structure/density changes, stop layers, and altered masking techniques. However, adjusting the die structure may not be possible due to specific design rules or issues relating to significant cost increases. The use of alternative masking techniques also adds extra steps to the fabrication process thereby further increasing costs and complexity.
Presently known techniques are unsatisfactory in correcting dishing and other irregular polishing processes in soft state-of-the-art materials. In addition to providing unsatisfactory results, these techniques also require the use of methods that are prohibitively costly or complex. Therefore, there is a need for apparatus and methods that will eliminate these effects, thereby permitting a higher degree of planarization and uniformity over the entire surface of the workpiece.